1. Technical Field
The present invention relates to a voltage-to-current converter circuit having transconductance (transfer conductance) with flat temperature characteristics, and in particular, relates to a differential amplifying type of voltage-to-current converter circuit having an output terminal with input offset voltage.
2. Related Art
A differential amplifying type of voltage-to-current converter circuit is often used in a differential amplifier, or a comparator that detects overvoltage, in a power conversion device. FIG. 3 shows an example of a configuration of this kind of heretofore known power conversion device.
FIG. 3 is a pulse width modulation (PWM) type step-down DC/DC converter wherein an output voltage Vo is generated from an input voltage VDD, and supplied to a load Z. The DC/DC converter includes a power source control semiconductor integrated circuit (IC) 1, an inductor L, a capacitor Co, an output terminal Vout, and resistors R10 and R20, which form a voltage setting feedback unit. Also, the power source control IC 1 includes an error amplifier ErrAMP, an oscillator OSC1 that generates a triangular wave Vosc, a PWM comparator PWMC, a P-channel metal oxide semiconductor field effect transistor (MOSFET) MP1 (hereafter, the P-channel MOSFET will be referred to as the P-channel MOS transistor MP1), which is a switching element, an N-channel MOSFET (hereafter referred to as the N-channel MOS transistor) MN1 as a synchronous rectification type commutating element, a drive circuit DRV that drives the P-channel MOS transistor MP1 and N-channel MOS transistor MN1 in accordance with the output of the PWM comparator PWMC, a reference voltage source Vref that generates a reference voltage Vref, a reference voltage source VHi that generates a reference voltage VHi, a comparator CMPHi, an overvoltage protection circuit 2, an input terminal FB, and an output terminal OUT.
The reference voltage Vref is input into the non-inverting input terminal of the error amplifier ErrAMP. An output signal Verr of the error amplifier ErrAMP is input into the non-inverting input terminal of the PWM comparator PWMC, while the triangular wave Vosc is input into the inverting input terminal. The PWM comparator PWMC compares the output signal Verr of the error amplifier ErrAMP and the triangular wave Vosc, and outputs a high (H) level signal when the signal level of the triangular wave Vosc is lower, and a low (L) level signal when the signal level of the triangular wave Vosc is higher, to the drive circuit DRV as a PWM signal. The drains of the P-channel MOS transistor MP1 and N-channel MOS transistor MN1 are connected to each other, and are connected to one end of the inductor L. Also, the sources of the P-channel MOS transistor MP1 and N-channel MOS transistor MN1 are connected to an input power source VDD and a ground potential (GND) respectively. The other end of the inductor L is connected to the output terminal Vout. The capacitor Co and a series circuit of the resistors R10 and R20 are connected in parallel between the output terminal Vout and GND. The potential of a connection point of the resistors R10 and R20 is input as a feedback signal Vfb into the inverting input terminal of the error amplifier ErrAMP via the input terminal FB. Also, the load Z is connected to the output terminal Vout as the load of the DC/DC converter.
Hereafter, a simple description will be given of an action of the DC/DC converter. The error amplifier ErrAMP inputs the signal Verr, wherein the difference between the reference voltage Vref and the feedback signal Vfb is amplified, into the PWM comparator PWMC. The PWM comparator PWMC, by comparing Verr and the triangular wave Vosc, outputs a square wave pulse (PWM signal) which, although of a constant cycle, is such that the ratio between H and L within one cycle changes in accordance with the output of the error amplifier ErrAMP, to the gate of the P-channel MOS transistor MP1 via the drive circuit DRV. That is, an output voltage V0 is kept constant by generating a square wave pulse such that the larger (smaller) (Vref−Vfb) is, the longer (shorter) a period for which the P-channel MOS transistor MP1 is on (conducts) within one cycle, thus increasing (decreasing) the energy accumulated in the inductor L. A square wave pulse is also output in the same way to the gate of the N-channel MOS transistor MN1. The square wave pulses output to the gates of the P-channel MOS transistor MP1 and N-channel MOS transistor MN1 are basically of the same phase but, in order to prevent the P-channel MOS transistor MP1 and N-channel MOS transistor MN1 being on simultaneously and a penetration current flowing, a dead time, which is a period for which both are off, is provided in the drive circuit DRV. When the DC/DC converter is operationally stable, the output voltage V0 becomes Vref×(R10+R20)/R20 owing to the inverting input terminal and non-inverting input terminal of the error amplifier ErrAMP being virtually short-circuited.
The reference voltage source VHi, comparator CMPHi, and overvoltage protection circuit 2 are for stopping the switching action of the DC/DC comparator when the output voltage V0 becomes abnormally high due to trouble occurring in the output line of the DC/DC converter. The value of the reference voltage VHi is higher than the reference voltage Vref, at a value to which the feedback signal Vfb does not rise during normal operation. When the feedback signal Vfb is higher than the reference voltage Vref, the comparator CMPHi inverts the output from low (L) to high (H). The overvoltage protection circuit 2 outputs a signal Stop that stops the switching action immediately on the output of the comparator CMPHi becoming H, or when the output H continues for a predetermined period. The drive circuit DRV, when the signal Stop is input from the overvoltage protection circuit 2, sends an H level signal to the gates of the P-channel MOS transistor MP1 and N-channel MOS transistor MN1, thus turning off the P-channel MOS transistor MP1 and turning on the N-channel MOS transistor MN1, and stopping the switching action, which is the main action of the DC/DC converter, on the safe side.
An example of a specific configuration of a voltage-to-current converter circuit that can be applied to the error amplifier ErrAMP and comparator CMPHi of the DC/DC converter shown in FIG. 3 is shown in JP-A-2006-174035 (FIG. 7, paragraphs [0002] to [0007], and the like). Also, as the voltage-to-current converter circuit needs a comparatively large area in the power source control IC (semiconductor integrated circuit) 1, it is preferable to reduce the number of voltage-to-current converter circuits in order to lower the cost of the control circuit (the power source control IC 1) in the power conversion device. FIG. 4 shows a two output voltage-to-current converter circuit configured based on the voltage-to-current converter circuit shown in JP-A-2006-174035 (FIG. 7, paragraphs [0002] to [0007], and the like).
The voltage-to-current converter circuit shown in FIG. 4 has a configuration including, between a high potential side power source potential VDD and a low potential side power source potential GND, a bias current source Ib0, a current mirror circuit formed of P-channel MOS transistors MP01 and MP02, a differential input unit formed of P-channel MOS transistors MP10 and MP11, a current mirror circuit formed of N-channel MOS transistors MN10 and MN11, a current mirror circuit formed of P-channel MOS transistors MP12, MP13, and MP14, and a current mirror circuit formed of N-channel MOS transistors MN12, MN13, and MN14. Also, 1, a, b, c, and d written below the reference numerals and signs affixed to the MOS transistors configuring the current mirror circuits represent the ratio of the input current or output current in the current mirror circuit. In this way, for example, it is shown that the mirror ratio (output current/input current) of the current mirror circuit formed of the N-channel MOS transistors MN10 and MN11 is 1, while the mirror ratio of the current mirror circuit formed of the P-channel MOS transistors MP12 and MP13 is a (=a/1). Also, characteristics of the P-channel MOS transistors MP10 and MP11 configuring the differential input unit are coordinated by arranging that size and manufacturing conditions are the same.
The bias current source Ib0 and current mirror circuit formed of the P-channel MOS transistors MP01 and MP02 are a circuit that supplies a constant bias current to the differential input unit formed of the P-channel MOS transistors MP10 and MP11, and the bias current is distributed to the N-channel MOS transistors MN11 and MN12 in accordance with the difference between two inputs IN+ and IN− input into the differential input unit. Taking the potentials of the inputs IN+ and IN− to be IN+ and IN− too, the sizes and manufacturing conditions of the P-channel MOS transistors MP01 and MP02 are assumed herein to be equivalent, meaning that, when IN+ is greater than IN−, the current flowing through MN11 is greater than the current flowing through MN12, while when IN+ is smaller than IN−, the current flowing through MN11 is smaller than the current flowing through MN12. The current flowing through the N-channel MOS transistor MN11 is set so as to be copied and fed back by the current mirror circuit formed of the N-channel MOS transistors MN10 and MN11 and the current mirror circuit formed of the P-channel MOS transistors MP12, MP13, and MP14, and discharged from the drains of the P-channel MOS transistors MP13 and MP14 further increased by a times and b times respectively. That is, the current mirror circuit formed of the P-channel MOS transistors MP12, MP13, and MP14 is a current source type current mirror circuit. Also, the current flowing through the N-channel MOS transistor MN12 is set so as to be copied and fed back by the current mirror circuit formed of the N-channel MOS transistors MN12, MN13, and MN14, and suctioned from the drains of the N-channel MOS transistors MN13 and MN14 further increased by c times and d times respectively. That is, the current mirror circuit formed of the N-channel MOS transistors MN12, MN13, and MN14 is a current sink type current mirror circuit.
The drain of the P-channel MOS transistor MP13 and the drain of the N-channel MOS transistor MN13 are connected to a first output terminal Out1 of the voltage-to-current converter circuit, while the drain of the P-channel MOS transistor MP14 and the drain of the N-channel MOS transistor MN14 are connected to a second output terminal Out2 of the voltage-to-current converter circuit. A current equivalent to the difference between the drain current of the P-channel MOS transistor MP13 and the drain current of the N-channel MOS transistor MN13 is output from the output terminal Out1, while a current equivalent to the difference between the drain current of the P-channel MOS transistor MP14 and the drain current of the N-channel MOS transistor MN14 is output from the output terminal Out2. Provided that nothing other than the gates of the MOS transistors is connected to the output terminals Out1 and Out2, the voltage of the output terminals Out1 and Out2 is directed to either the high potential side power source potential VDD or the low potential side power source potential GND, with a point at which the output current reaches zero as a dividing line, meaning that the voltage-to-current converter circuit can be utilized as a comparator or an operational amplifier.
Herein, assuming that a=c, the input offset voltage relating to the output from the output terminal Out1 is zero (the output current from the output terminal Out1 is zero when IN+=IN−). Meanwhile, with regard to the output terminal Out2, assuming that b≠d, the input offset voltage relating to the output of the output terminal Out2 does not become zero. That is, the output of the output terminal Out2 has a positive input offset voltage when b is greater than d (assuming the absolute value of the offset voltage to be ofsv (>0), the output current from the output terminal Out1 is zero when (IN−)=(IN+)+ofsv), and has a negative input offset voltage when b is smaller than d (the output current from the output terminal Out1 is zero when (IN−)=(IN+)−ofsv). Utilizing this, assuming that b is greater than d, it is possible to combine the two voltage-to-current converter circuits shown in FIG. 3 in one by inputting the feedback signal Vfb of FIG. 3 into IN+ and inputting the reference voltage Vref into IN−, and thus possible to lower the cost of the control circuit. In this case, the reference voltage VHi of FIG. 3 is obtained by VHi=Vref+ofsv.
Considering the temperature characteristics of the voltage-to-current converter circuit of FIG. 4, firstly, the transconductance of the differential input unit (=(the difference between the drain currents of the two transistors configuring the differential input unit)/(the difference between the two input voltages)) are determined by the transconductance of the P-channel MOS transistors MP10 and MP11 configuring the differential input unit, wherein the transconductance of the MOS transistors depends on the bias current and the size of the MOS transistors, and has negative temperature characteristics. With regard to whether the temperature characteristics are positive or negative, they are taken to be positive when the absolute value of a characteristic value indicating the temperature characteristics rises along with the temperature, and negative when the absolute value of the characteristic value decreases on the temperature rising. Consequently, the transconductance of the differential input unit also has negative temperature characteristics. Also, when providing an input offset voltage by adjusting the mirror ratio of the current mirror circuits, as with the output terminal Out2, the input offset voltage also has temperature characteristics. When a voltage-to-current converter circuit wherein the differential input unit transconductance and input offset voltage have temperature characteristics is applied to the kind of DC/DC converter shown in FIG. 3, the stability of a feedback loop and an overvoltage protection threshold value voltage in the DC/DC converter are temperature-dependent, which is not desirable in terms of the stability of the DC/DC converter.
With regard to the case of the output terminal Out2, as a similar circuit, there is known a method whereby the temperature characteristics of a fixed current circuit that outputs a fixed current by combining a source type current mirror circuit and a sink type current mirror circuit are caused to be zero (for example, refer to JP-A-62-251816), but no method has been known whereby the output current value is variable, and the temperature characteristics are zero along with those of the differential input unit.